1. Technical Field
This invention relates to data communication systems. More particularly, this invention elates to LVDS data recovery in a receiving system of digital data transmitted via a high-speed ink.
2. Description of the Related Art
High-speed low voltage differential swing (LVDS) interfaces have become popular to use as display interfaces, especially for flat panel displays. By using an LVDS interface, the electromagnetic interference (EMI) level of computer systems may be sufficiently reduced to allow a computer system to pass current commercial EMI compliance limits. However, current commercial LVDS chip sets suffer from insufficient bandwidth; for example, many do not even have enough bandwidth to support XGA resolution, which is 455 Mbps (65 MHzxc3x977).
The main limitation on the required bandwidth is caused by timing skew. Skew is primarily caused by cable and board line length mismatches. The situation is aggravated as the cable length and the required bandwidth increases. Unless skew is properly corrected or managed, the required bandwidth cannot be met. Therefore, a skew-managing scheme for LVDS interface is needed which can remove the timing skew between data and clock channels, and thereby increase the maximum bandwidth of the system and enhance compatibility among LVDS chip sets.
In accordance with the present invention, a skew-managing scheme for an LVDS system s disclosed to provide greater bandwidth for LVDS systems.
An apparatus for correcting skew between data signals and a clock signal in a system where the data and clock signals are transmitted using low-voltage differential swing is disclosed. The apparatus comprises, in one embodiment, a delay locked loop, for converting the LVDS clock signal into a full-swing clock signal, and a plurality of data recovery channels, each channel coupled to a data signal and comprising an LVDS converter, a skew adjust circuit, a sampler array, and a phase adjusting circuit. The delay locked loop and the data channel circuitry combine to remove skew from LVDS signals by generating multiple clock signals, sampling the data at multiple intervals, using the samples to eliminate skew, and retrieving correct data samples from the data signals.
In another embodiment, the sampler array comprises a plurality of transition sampling circuits, for sampling transitions between two adjacent serial bits of data and generating a lock signal and a sampled data signal responsive to the sampled transition, and a plurality of center sampling circuits, for sampling a center point of each serial bit of data and generating a center sample signal responsive to the sample, and the phase adjusting circuit for generating skew control signals responsive to the center sample signals, lock signals, and transition data signals received from the sampler array.